Enhanced frame grabber with high-speed interfaces
Silicon Software's microEnable 5 "ironman" is a family of high performance digital frame grabbers for CoaXPress, CameraLink and CameraLink HS cameras. They are based on the PCI Express bus technology for the PC and implemented with a PCIe x8 (Gen2) bus interface. The cost saving frame grabber family, microEnable 5 "marathon" is based on PCI Express x4 (Gen 2) bus interface.
The microEnable 5 CameraLink frame grabbers support onboard real-time high quality colour reconstruction for high-end and high-speed colour line scan and area scan applications. The CameraLink interface is capable of running with a bandwidth of up to 3.6 GByte/s with unique features and benefits for demanding applications - especially in high-end print applications and web and surface inspection with high quality colour reconstruction.
The load on the host CPU is reduced as a lot of the preprocessing is handled by the frame grabber. Another interesting feature is the ability to capture data from four cameras with a single frame grabber. This helps to save costs on technical infrastructure, as fewer components are required.
Using the powerful Visual Applets software ensures fast and flexible programming of the FPGAs on the Silicon Software frame grabbers. This graphical design environment requires no special hardware programming know-how and frees up valuable development time for your application.
As a certified Visual Applets partner STEMMER IMAGING can create individual Visual Applets designs. This allows you to free up resources and focus on your core business.
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| Model | Number of cameras (max) | Power over data interface | Inputs | PC-interface | Interface/Standard |
| SISO MICROENABLE 5 - AD8-PoCL | 1 | yes | Full, Deca | PCIe x8 (Gen 2) | CameraLink |
| SISO MICROENABLE 5 - AQ8-CXP6D | 4 | yes | CXP-1, CXP-2, CXP-3, CXP-5, CXP-6 | PCIe x8 (Gen 2) | CoaXPress |
| SISO MICROENABLE 5 - VD8-PoCL | 1 | yes | Full, Deca | PCIe x8 (Gen 2) | CameraLink |
| SISO MICROENABLE 5 - VQ8-CXP6D | 4 | yes | CXP-1, CXP-2, CXP-3, CXP-5, CXP-6 | PCIe x8 (Gen 2) | CoaXPress |
| SISO MICROENABLE 5 MARATHON ACL | 2 | yes | Full, Deca, Base, Medium | PCIe x4 (Gen 2) | |
| SISO MICROENABLE 5 MARATHON ACX DP | 2 | yes | CXP-1, CXP-2, CXP-3, CXP-5, CXP-6 | PCIe x4 (Gen 2) | CoaXPress |
| SISO MICROENABLE 5 MARATHON ACX QP | 4 | yes | CXP-1, CXP-2, CXP-3, CXP-5, CXP-6 | PCIe x4 (Gen 2) | CoaXPress |
| SISO MICROENABLE 5 MARATHON ACX SP | 1 | yes | CXP-1, CXP-2, CXP-3, CXP-5, CXP-6 | PCIe x4 (Gen 2) | CoaXPress |
| SISO MICROENABLE 5 MARATHON AF2 | 2 | no | Dual CLHS F2 | PCIe x4 (Gen 2) | CameraLink HS |
| SISO MICROENABLE 5 MARATHON VCL | 2 | yes | Full, Deca, Base, Medium | PCIe x4 (Gen 2) | |
| SISO MICROENABLE 5 MARATHON VCLx | |||||
| SISO MICROENABLE 5 MARATHON VCX QP | 4 | yes | CXP-1, CXP-2, CXP-3, CXP-5, CXP-6 | PCIe x4 (Gen 2) | CoaXPress |
| SISO MICROENABLE 5 MARATHON VF2 | 2 | no | Dual CLHS F2 | PCIe x4 (Gen 2) | CameraLink HS |
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TTL Triggerboard for microEnable 4 and 5 series
Optocoupled trigger extension board for microEnable 4 and 5 series
| File | Topics | Size | ||
| Silicon Software microEnable 5 Ironman AD8-PoCL | Data sheets |
2.0 MB |
||
| Silicon Software microEnable 5 Ironman AQ8-CXP6D | Data sheets |
2.0 MB |
||
| Silicon Software microEnable 5 Ironman VD8-PoCL | Data sheets |
2.0 MB |
||
| Silicon Software microEnable 5 Ironman VQ8-CXP6D | Data sheets |
2.0 MB |
||
| Silicon Software microEnable 5 Marathon ACL | Data sheets |
1.9 MB |
||
| Silicon Software microEnable 5 Marathon ACX-QP | Data sheets |
1.9 MB |
||
| Silicon Software microEnable 5 Marathon ACX-SP | Data sheets |
1.6 MB |
||
| Silicon Software microEnable 5 Marathon AF2 | Data sheets |
1.9 MB |
||
| Silicon Software microEnable 5 Marathon VCL | Data sheets |
1.9 MB |
||
| Silicon Software microEnable 5 Marathon VCLx | Data sheets |
1.6 MB |
||
| Silicon Software microEnable 5 Marathon VF2 | Data sheets |
1.9 MB |
||
| Silicon Software microEnable 5 Marathon deep VCL | Data sheets |
2.1 MB |
